Difference between revisions of "Power ISA"

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|+Key to Version column in Power ISA 3.0B instruction list
 
|+Key to Version column in Power ISA 3.0B instruction list
 
!Code
 
!Code
−
!Explanation
+
!Released
 +
!Specification
 +
!Compliant cores
 
|-
 
|-
−
|P1||Instruction introduced in the POWER Architecture.
+
|P1
 +
|
 +
|POWER Architecture
 +
|
 
|-
 
|-
−
|P2||Instruction introduced in the POWER2 Architecture.
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|P2
 +
|
 +
|POWER2 Architecture
 +
|
 
|-
 
|-
−
|PPC||Instruction introduced in the PowerPC Architecture prior to v2.00.
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|PPC
 +
|
 +
|PowerPC Architecture prior to v2.00
 +
|
 
|-
 
|-
−
|v2.00||Instruction introduced in the PowerPC Architecture Version 2.00.
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|v2.00
 +
|
 +
|PowerPC Architecture v2.00
 +
|POWER4
 
|-
 
|-
−
|v2.01||Instruction introduced in the PowerPC Architecture Version 2.01.
+
|v2.01
 +
|December 2003
 +
|[[:Category:PowerPC Architecture v2.01|PowerPC Architecture v2.01]]
 +
|POWER4+, PPC970
 
|-
 
|-
−
|v2.02||Instruction introduced in the PowerPC Architecture Version 2.02.
+
|v2.02
 +
|February 2005
 +
|[[:Category:PowerPC Architecture v2.02|PowerPC Architecture v2.02]]
 +
|POWER5, Cell PPE
 
|-
 
|-
−
|v2.03||Instruction introduced in the Power ISA Architecture Version 2.03.
+
|v2.03
 +
|September 2006
 +
|[[:File:PowerISA_V2.03_Final_Public.pdf|Power ISA v2.03]]
 +
|[[PPC405]], PPC440, PPC460, e200, e500, POWER5+
 
|-
 
|-
−
|v2.04||Instruction introduced in the Power ISA Architecture Version 2.04.
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|v2.04
 +
|April 2007
 +
|[[:File:PowerISA_V2.04-FINAL.Public.pdf|Power ISA v2.04]]
 +
|POWER5++, PA6T
 
|-
 
|-
−
|v2.05||Instruction introduced in the Power ISA Architecture Version 2.05.
+
|v2.05
 +
|October 2007
 +
|[[:File:PowerISA_V2.05.pdf|Power ISA v2.05]]
 +
|POWER6
 
|-
 
|-
−
|v2.06||Instruction introduced in the Power ISA Architecture Version 2.06.
+
|v2.06
 +
|January 2009
 +
|[[:File:PowerISA_V2.06_PUBLIC.pdf| Power ISA v2.06]]
 +
|e5500, POWER7
 
|-
 
|-
−
|v2.07||Instruction introduced in the Power ISA Architecture Version 2.07.
+
|v2.06B
 +
|July 2010
 +
|[[:File:PowerISA_V2.06B_V2_PUBLIC.pdf| Power ISA v2.06B]]
 +
|
 
|-
 
|-
−
|v3.0||Instruction introduced in the Power ISA Architecture Version 3.0.
+
|v2.07
 +
|May 2013
 +
|[[:File:PowerISA_V2.07_PUBLIC.pdf| Power ISA v2.07]]
 +
|e6500, [[POWER8]]
 
|-
 
|-
−
|v3.0B||Instruction introduced in the Power ISA Architecture Version 3.0B.
+
|v2.07B
 +
|April 2015
 +
|[[:File:PowerISA_V2.07B.pdf| Power ISA v2.07B]]
 +
|
 +
|-
 +
|v3.0
 +
|November 2015
 +
|[[:File:PowerISA_V3.0.pdf| Power ISA v3.0]]
 +
|
 +
|-
 +
|v3.0B
 +
|March 2017
 +
|[[:File:PowerISA_public.v3.0B.pdf| Power ISA v3.0B]]
 +
|[[POWER9]]
 
|}
 
|}
  
−
== Privilege Levels ==
+
== See also ==
  
−
* ultravisor privileged state
+
* [[Power ISA/Privilege States|Power ISA/Privilege States]]
−
* hypervisor privileged state
+
* [[Power ISA/Machine State Register|Power ISA/Machine State Register]]
−
* privileged state / supervisor mode
+
* [[Power ISA/Vector Operations|Power ISA/Vector Operations]]
−
* problem state / user mode
 
  
−
At the moment very little information exists about the ultravisor state. It is not mentioned only in Power ISA version 2.07 documents at all, and version 3.0B only mentions it as a possible classification for instructions.
+
== External Links ==
  
−
{| class="wikitable sortable"
+
* [https://www.ibm.com/systems/power/openpower/posting.xhtml?postingId=01F8EF905EC4A2CD85257EAF0069612D Power ISA at IBM OpenPOWER portal]
−
|+Privilege Classification of Instructions in Power ISA
 
−
!Code
 
−
!2.07
 
−
!3.0B
 
−
!Description
 
−
|-
 
−
|P
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|a privileged instruction.
 
−
|-
 
−
|O
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|an instruction that is treated as privileged or nonprivileged (or hypervisor, for mtspr), depend-
 
−
ing on the SPR or PMR number.
 
−
|-
 
−
|PI
 
−
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|an instruction that is illegal in privileged state.
 
−
|-
 
−
|H
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|an instruction that can be executed only in hypervisor state
 
−
|-
 
−
|PH
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
−
|a hypervisor privileged instruction if Category Embedded.Hypervisor is implemented; otherwise
 
−
denotes a privileged instruction.
 
−
|-
 
−
|M
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
−
|an instruction that is treated as privileged or nonprivileged, depending on the value of the UCLE
 
−
bit in the MSR
 
−
|-
 
−
|U
 
−
|style="background:#F99;vertical-align:middle;text-align:center;"|No
 
−
|style="background:#9F9;vertical-align:middle;text-align:center;"|Yes
 
−
|an instruction that can be executed only in ultravisor state
 
−
|}
 
  
−
== External Links ==
+
* [https://en.wikipedia.org/wiki/Power_ISA Power ISA English Wikipedia page]
  
−
* [https://www.ibm.com/systems/power/openpower/posting.xhtml?postingId=01F8EF905EC4A2CD85257EAF0069612D Power ISA at IBM OpenPOWER portal]
+
[[Category:Power Architecture]]

Revision as of 07:37, 19 September 2019

Power ISA is the specification for how Power architecture processors are to behave. It dictates the machine instructions available, and exactly how they are to process given data.

There are two primary versions of the Power ISA that are of interest to PowerNV platforms:

History

The Power ISA evolved from the PowerPC ISA which in turn was an evolution of the POWER ISA used by POWER1 and POWER2 chips.

POWER ISA → PowerPC ISA → Power ISA

When the Power ISA 3.0B specification lists all available instructions, it specifically mentions what version of which architecture introduced the instruction; this gives a fairly quick history of the ISA itself:

Key to Version column in Power ISA 3.0B instruction list
Code Released Specification Compliant cores
P1 POWER Architecture
P2 POWER2 Architecture
PPC PowerPC Architecture prior to v2.00
v2.00 PowerPC Architecture v2.00 POWER4
v2.01 December 2003 PowerPC Architecture v2.01 POWER4+, PPC970
v2.02 February 2005 PowerPC Architecture v2.02 POWER5, Cell PPE
v2.03 September 2006 Power ISA v2.03 PPC405, PPC440, PPC460, e200, e500, POWER5+
v2.04 April 2007 Power ISA v2.04 POWER5++, PA6T
v2.05 October 2007 Power ISA v2.05 POWER6
v2.06 January 2009 Power ISA v2.06 e5500, POWER7
v2.06B July 2010 Power ISA v2.06B
v2.07 May 2013 Power ISA v2.07 e6500, POWER8
v2.07B April 2015 Power ISA v2.07B
v3.0 November 2015 Power ISA v3.0
v3.0B March 2017 Power ISA v3.0B POWER9

See also

External Links

Retrieved from "https://wiki.raptorcs.com/w/index.php?title=Power_ISA&oldid=2731"