Difference between revisions of "POWER9"
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== Chips ==
== Chips ==
, Scale Up
[[|]][[|]]and [] , to .
Chips be [] [] ;the , , .<ref>Stuecheli, Jeff. POWER9. Presentation for [https://www.ibm.com/developerworks/community/wikis/home?lang=en#!/wiki/Power+Systems/page/AIX+Virtual+User+Group+-+USA AIX VUG]. ([https://public.dhe.ibm.com/systems/power/community/aix/Central-VUG-Replays/2017-01-26_IBM_POWER9.wmv video download], [https://www.ibm.com/developerworks/community/wikis/form/anonymous/api/wiki/61ad9cf2-c6a3-4d2c-b779-61ff0266d32a/page/1cb956e8-4160-4bea-a956-e51490c2b920/attachment/56cea2a9-a574-4fbb-8b2c-675432367250/media/POWER9-VUG.pdf slides], [[User:Torpcoms/Timemark/POWER9|timemarks]])</ref>
=== Markings ===
=== Markings ===
Revision as of 18:37, 6 March 2019
|Maximum cores||12 SMT8 / 24 SMT4|
|L2 cache / slice||512kB|
|L3 cache / slice||10MB|
|Production availability||January 2018|
|← POWER8E||POWER10 →|
POWER9 is IBM's most recent POWER compatible server and workstation CPU (POWER ISA v3.0B). Built on a 14nm process, each CPU package can contain up to 24 SMT4 cores or 12 SMT8 cores. Each pair of SMT4 cores, or singleton SMT8 core, comprises a slice; each slice in turn contains 512kB L2 cache and 10MB L3 cache. Raptor Computing Systems' 4- and 8-core processors provide unpaired cores, such that one SMT4 core per slice is fused off. This allows each of the SMT4 cores to utilize the full cache of the slice exclusively, increasing performance for these ST-focused processors.
There are three known silicon masks of POWER9:
Chips can be fused as SMT4 or SMT8 during manufacturing. The SMT8 variant essentially fuses each pair of cores into one “core”, halving the core count while doubling the number of threads per core. SMT4 variants are intended for PowerNV platforms running Linux, and SMT8 variants are intended for use with IBM's PowerVM hypervisor which can run Linux, AIX or IBM i.
Part numbers for different POWER9 Sforza SKUs can be found on page 58 of the datasheet. These part numbers are printed on the surface of the CPU module and can be used to determine the type of the CPU.
Nimbus chips are available in three different modules: Sforza, Monza, and LaGrange. Each module exposes different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers.
Sforza is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what Talos™ II uses for maximal similarity to existing desktop, workstation, and server systems.
Monza modules offer the most OpenCAPI/NVLink bandwidth and are used in IBM's AC922 (Witherspoon) systems, such as those used by the Sierra and Summit supercomputers.
Little is known about Cumulus chips now; as Scale Up chips, they will trade some peripherals bandwidth for communication between more than 2 sockets.
- POWER9 CPU and Platform Documentation
- POWER9 Hardware Compatibility List
- Basic POWER9 overview presentation
- Power ISA version 3.0B - implemented by POWER9