Difference between revisions of "POWER9"

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== Chips ==
 
== Chips ==
  
{| class="wikitable"
+
There are three known silicon masks of POWER9:
|+ POWER9 Chips
+
* Nimbus (POWER9, [[Scale Out]])
!  !! PowerNV !! PowerVM
+
* Cumulus (POWER9, [[Scale Up]])
|-
+
* Axon (POWER9, unknown)
! Scale Out
 
| Nimbus || unknown<ref group="note">The presentation by Jeff Stuecheli makes it clear that these chips will exist, but the codename for them is currently unknown.</ref>
 
|-
 
! Scale Up
 
| || Cumulus
 
|}
 
<references group="note"/>
 
  
[[PowerNV|PowerNV]] chips use [[SMT4|SMT4]] cores exclusively, and are intended to run Linux on bare metal as an OpenPOWER system. PowerVM chips, in contrast, use [[SMT8|SMT8]] cores, and are intended to run Linux, AIX, or IBM i under IBM's PowerVM hypervisor.
+
Nimbus is the &#8220;[[Scale Out|scale out]]&#8221; variant and uses direct-attach DDR4 memory. Cumulus is the &#8220;[[Scale Up|scale up]]&#8221; version and uses [[Centaur]] memory buffers, allowing larger amounts of memory to be attached to a system.
  
Chips are planned to be made in both [[Scale Out|Scale Out]] (direct-attach RAM) and [[Scale Up|Scale Up]] (centaur-buffered RAM) configurations; where a Scale Out system can use normal RAM attached directly to the CPU, Scale Up chips require that access to RAM be through a Centaur memory buffer, which behaves like a L4 cache.<ref>Stuecheli, Jeff. POWER9. Presentation for [https://www.ibm.com/developerworks/community/wikis/home?lang=en#!/wiki/Power+Systems/page/AIX+Virtual+User+Group+-+USA AIX VUG]. ([https://public.dhe.ibm.com/systems/power/community/aix/Central-VUG-Replays/2017-01-26_IBM_POWER9.wmv video download], [https://www.ibm.com/developerworks/community/wikis/form/anonymous/api/wiki/61ad9cf2-c6a3-4d2c-b779-61ff0266d32a/page/1cb956e8-4160-4bea-a956-e51490c2b920/attachment/56cea2a9-a574-4fbb-8b2c-675432367250/media/POWER9-VUG.pdf slides], [[User:Torpcoms/Timemark/POWER9|timemarks]])</ref>
+
Chips can be fused as [[SMT4]] or [[SMT8]] during manufacturing. The [[SMT8]] variant essentially fuses each pair of cores into one &#8220;core&#8221;, halving the core count while doubling the number of threads per core. [[SMT4]] variants are intended for [[PowerNV]] platforms running Linux, and [[SMT8]] variants are intended for use with IBM's PowerVM hypervisor which can run Linux, AIX or IBM i.<ref>Stuecheli, Jeff. POWER9. Presentation for [https://www.ibm.com/developerworks/community/wikis/home?lang=en#!/wiki/Power+Systems/page/AIX+Virtual+User+Group+-+USA AIX VUG]. ([https://public.dhe.ibm.com/systems/power/community/aix/Central-VUG-Replays/2017-01-26_IBM_POWER9.wmv video download], [https://www.ibm.com/developerworks/community/wikis/form/anonymous/api/wiki/61ad9cf2-c6a3-4d2c-b779-61ff0266d32a/page/1cb956e8-4160-4bea-a956-e51490c2b920/attachment/56cea2a9-a574-4fbb-8b2c-675432367250/media/POWER9-VUG.pdf slides], [[User:Torpcoms/Timemark/POWER9|timemarks]])</ref>
  
 
=== Markings ===
 
=== Markings ===

Revision as of 18:37, 6 March 2019

Processor Information
POWER9
Power ISA 3.0B
Process node 14nm
Maximum slices 24
Maximum cores 12 SMT8 / 24 SMT4
L2 cache / slice 512kB
L3 cache / slice 10MB
Production availability January 2018
Production stepping(s) DD2.2
← POWER8E POWER10 →

POWER9 is IBM's most recent POWER compatible server and workstation CPU (POWER ISA v3.0B). Built on a 14nm process, each CPU package can contain up to 24 SMT4 cores or 12 SMT8 cores. Each pair of SMT4 cores, or singleton SMT8 core, comprises a slice; each slice in turn contains 512kB L2 cache and 10MB L3 cache. Raptor Computing Systems' 4- and 8-core processors provide unpaired cores, such that one SMT4 core per slice is fused off. This allows each of the SMT4 cores to utilize the full cache of the slice exclusively, increasing performance for these ST-focused processors.

Chips

There are three known silicon masks of POWER9:

Nimbus is the “scale out” variant and uses direct-attach DDR4 memory. Cumulus is the “scale up” version and uses Centaur memory buffers, allowing larger amounts of memory to be attached to a system.

Chips can be fused as SMT4 or SMT8 during manufacturing. The SMT8 variant essentially fuses each pair of cores into one “core”, halving the core count while doubling the number of threads per core. SMT4 variants are intended for PowerNV platforms running Linux, and SMT8 variants are intended for use with IBM's PowerVM hypervisor which can run Linux, AIX or IBM i.[1]

Markings

Part numbers for different POWER9 Sforza SKUs can be found on page 58 of the datasheet. These part numbers are printed on the surface of the CPU module and can be used to determine the type of the CPU.

Modules

POWER9 Modules
Chip Module
Nimbus Sforza
Monza
LaGrange
(PowerVM
Scale Out)
unknown
Cumulus unknown

Nimbus

Nimbus chips are available in three different modules: Sforza, Monza, and LaGrange. Each module exposes different I/O functionality to the host platform, allowing purpose-built systems to be constructed in addition to more general-purpose computers.

Sforza

Sforza is the most flexible of these packages, providing PCIe 4.0 lanes as the main I/O resource, and is what Talos™ II uses for maximal similarity to existing desktop, workstation, and server systems.

Monza

Monza modules offer the most OpenCAPI/NVLink bandwidth and are used in IBM's AC922 (Witherspoon) systems, such as those used by the Sierra and Summit supercomputers.

LaGrange

LaGrange modules offer increased XBus bandwidth between processor sockets and are used by the Google/Rackspace Zaius motherboard used in the Barreleye G2 system.[2]

Cumulus

Little is known about Cumulus chips now; as Scale Up chips, they will trade some peripherals bandwidth for communication between more than 2 sockets.[3]

References

  1. Stuecheli, Jeff. POWER9. Presentation for AIX VUG. (video download, slides, timemarks)
  2. Gangidi, Adi Zaius/Barreleye G2 Server Development Update. 2017-11-13
  3. Morgan, Timothy Prickett. POWER9 to the People. 2017-12-05

Resources

External Links