POWER8E

From RCS Wiki
Revision as of 14:17, 2 March 2019 by HLandau (talk | contribs)
Jump to navigation Jump to search
Processor Information
POWER8E
Power ISA 2.07
Process node 22nm
Maximum slices 12
Maximum cores 12 SMT8
L2 cache / slice 512kB
L3 cache / slice 8MB
Production availability 2016
Production stepping(s) DD2.1
← POWER8 POWER9 →

POWER8E (also known as POWER8 with NVLink, 8335-GTB POWER8, or POWER8+) processors have a different socket than standard POWER8 chips.

Compared to a standard POWER8 Single Chip Module (SCM), the POWER8 with NVLink modifies:

  • 2nd CAPP unit added, X2 removed
  • x8 PHB
  • x8 IOP
  • A-bus removed, NVLink added
  • NVLink support added in extended ES
  • Chip height: 2 C4 rows added

Without A-bus or SMP over PCIe, the processors in a multisocket configuration instead use X-Bus for SMP. The chip size is 659 mm2, rather than 649 mm2 for POWER8, and only available for the S822LC for HPC, specifically the 8335-GTB model. [1][2]

External Links

References

  1. Caldeira, Alexandre Bicas; Haug, Volker. IBM Power System S822LC for High Performance Computing Introduction and Technical Overview (PDF). IBM Redpaper. ISBN 9780738455617.
  2. Gupta, Sumit. IBM & NVIDIA present the NVLink server you’ve been waiting for (HTML). 2016-09-08. IBM IT Infrastructure Blog.