Difference between revisions of "POWER8E"
Jump to navigation
Jump to search
(add wikipedia link) |
(add redpapers info) |
||
| Line 22: | Line 22: | ||
}} | }} | ||
| − | POWER8 processors with NVLink. | + | POWER8 processors with NVLink. These have a different socket than standard POWER8 chips. |
| + | |||
| + | Compared to standard POWER8, the POWER8 with NVLink modifies:<ref>Caldeira, Alexandre Bicas; Haug, Volker. [https://www.redbooks.ibm.com/redpapers/pdfs/redp5405.pdf IBM Power System S822LC for High Performance Computing Introduction and Technical Overview] (PDF). IBM Redpaper. ISBN 9780738455617.</ref> | ||
| + | |||
| + | * 2<sup>nd</sup> CAPP unit added, X2 removed | ||
| + | * x8 PHB | ||
| + | * x8 IOP | ||
| + | * A-bus removed, NVLink added | ||
| + | * NVLink support added in extended ES | ||
| + | * Chip height: 2 C4 rows added | ||
== External Links == | == External Links == | ||
| Line 28: | Line 37: | ||
* [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER8_with_NVIDIA_NVLink POWER8 with NVLink at IBM OpenPOWER portal] | * [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER8_with_NVIDIA_NVLink POWER8 with NVLink at IBM OpenPOWER portal] | ||
* [https://en.wikipedia.org/wiki/POWER8#POWER8_with_NVLink POWER8 with NVLink section of Wikipedia POWER8 article] | * [https://en.wikipedia.org/wiki/POWER8#POWER8_with_NVLink POWER8 with NVLink section of Wikipedia POWER8 article] | ||
| + | |||
| + | == References == | ||
| + | <references/> | ||
Revision as of 14:20, 3 January 2018
| POWER8E | |
|---|---|
| POWER ISA | 2.07 |
| Process node | 22nm |
| Maximum slices | 12 |
| Maximum cores | 12 SMT8 |
| L2 cache / slice | 512kB |
| L3 cache / slice | 8MB |
| Production availability | 2016 |
| Production stepping(s) | DD2.1 |
| ← POWER8 | POWER9 → |
POWER8 processors with NVLink. These have a different socket than standard POWER8 chips.
Compared to standard POWER8, the POWER8 with NVLink modifies:[1]
- 2nd CAPP unit added, X2 removed
- x8 PHB
- x8 IOP
- A-bus removed, NVLink added
- NVLink support added in extended ES
- Chip height: 2 C4 rows added
External Links
References
- ↑ Caldeira, Alexandre Bicas; Haug, Volker. IBM Power System S822LC for High Performance Computing Introduction and Technical Overview (PDF). IBM Redpaper. ISBN 9780738455617.
