Difference between revisions of "OpenPOWER Firmware"

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(→‎Components: linking both mentions of SEEPROM in Loaded from column, since sort order is unknown)
(→‎Components: continuing previous edits; moving source links to firmware column,)
Line 11: Line 11:
 
! Function
 
! Function
 
|-
 
|-
−
| [[OTPROM|OTPROM]]
+
| SBE - OTPROM
−
| SBE core (on CPU chip)
 
−
| eFuses (on CPU module)
 
 
[https://git.raptorcs.com/git/talos-sbe/tree/src/boot/otprom_init.S Source]
 
[https://git.raptorcs.com/git/talos-sbe/tree/src/boot/otprom_init.S Source]
−
|
+
| [[Self-Boot Engine|SBE]] core (on CPU)
 +
| [[OTPROM|OTPROM]] (on CPU die)
 +
| The portion of [[Self-Boot Engine|Self-Boot Engine]] (SBE) firmware permanently written via eFuses into the POWER9 silicon's OTPROM
 
* very first instructions executed
 
* very first instructions executed
−
* loads SBE firmware from SEEPROM into SBE core
+
* loads remaining SBE firmware from SEEPROM into SBE core
 
|-
 
|-
−
| [[Self-Boot Engine|Self-Boot Engine]] (SBE) firmware
+
| SBE - SEEPROM  
−
| SBE core (on CPU chip)
 
−
| SBE [[SEEPROM|SEEPROM]] (on CPU module)
 
 
[https://git.raptorcs.com/git/talos-sbe/tree/ Source]
 
[https://git.raptorcs.com/git/talos-sbe/tree/ Source]
−
|
+
| [[Self-Boot Engine|SBE]] core (on CPU)
 +
| SBE [[SEEPROM|SEEPROM]] (on CPU)
 +
| The portion of [[Self-Boot Engine|Self-Boot Engine]] (SBE) firmware run from rewritable [[SEEPROM|SEEPROM]]
 
* initialises CPU core
 
* initialises CPU core
 
* loads Hostboot Bootloader
 
* loads Hostboot Bootloader
Line 29: Line 29:
 
|-
 
|-
 
| Hostboot Bootloader (HBBL)
 
| Hostboot Bootloader (HBBL)
 +
[https://git.raptorcs.com/git/talos-hostboot/tree/src/bootloader Source]
 
| CPU core
 
| CPU core
−
| SBE [[SEEPROM|SEEPROM]] (on CPU chip)
+
| SBE [[SEEPROM|SEEPROM]] (on CPU)
−
[https://git.raptorcs.com/git/talos-hostboot/tree/src/bootloader Source]
 
 
|
 
|
 
* first code which runs on main CPU cores; loads and executes rest of Hostboot
 
* first code which runs on main CPU cores; loads and executes rest of Hostboot
Line 37: Line 37:
 
|-
 
|-
 
| [[Hostboot|Hostboot]]
 
| [[Hostboot|Hostboot]]
 +
[https://git.raptorcs.com/git/talos-hostboot/tree/ Source]
 
| CPU core
 
| CPU core
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-hostboot/tree/ Source]
 
 
|
 
|
 
* initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
 
* initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
Line 45: Line 45:
 
|-
 
|-
 
| [[Skiboot|Skiboot]]
 
| [[Skiboot|Skiboot]]
 +
[https://git.raptorcs.com/git/talos-skiboot/tree/ Source]
 
| CPU core
 
| CPU core
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-skiboot/tree/ Source]
 
 
|
 
|
 
* initialises PCIe controllers, device trees, real time clock, NVlink, sensors
 
* initialises PCIe controllers, device trees, real time clock, NVlink, sensors
Line 55: Line 55:
 
|-
 
|-
 
| [[Skiroot]]/[[Petitboot|Petitboot]]
 
| [[Skiroot]]/[[Petitboot|Petitboot]]
 +
[https://git.raptorcs.com/git/talos-petitboot/ Source]
 
| CPU core
 
| CPU core
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-petitboot/ Source]
 
 
|
 
|
 
* [[Skiroot]] refers to the Linux kernel and initramfs which runs from RAM
 
* [[Skiroot]] refers to the Linux kernel and initramfs which runs from RAM
Line 64: Line 64:
 
|-
 
|-
 
| OCC firmware
 
| OCC firmware
−
| [[On-Chip Controller|OCC]] core (on CPU chip)
+
[https://git.raptorcs.com/git/talos-occ/tree/ Source]
 +
| [[On-Chip Controller|OCC]] core (on CPU)
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-occ/tree/ Source]
 
 
| The [[On-Chip Controller|On-Chip Controller]] (OCC) manages:
 
| The [[On-Chip Controller|On-Chip Controller]] (OCC) manages:
 
* thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
 
* thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
 
|-
 
|-
 
| CME [[HCODE]]
 
| CME [[HCODE]]
−
| [[CME]] cores (on CPU chip)
+
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
| [[CME]] cores (on CPU)
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 
 
| The [[Core Management Engine|Core Management Engines]] (CME) are auxillary cores used for power management purposes. They are ultimately responsible to the OCC.
 
| The [[Core Management Engine|Core Management Engines]] (CME) are auxillary cores used for power management purposes. They are ultimately responsible to the OCC.
 
* There is one CME for every pair of SMT4 cores.
 
* There is one CME for every pair of SMT4 cores.
 
|-
 
|-
 
| SGPE and PGPE [[HCODE]]
 
| SGPE and PGPE [[HCODE]]
−
| [[SGPE]] and [[PGPE]] cores (on CPU chip)
+
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
| [[SGPE]] and [[PGPE]] cores (on CPU)
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 
 
| [[GPE|General Purpose Engine]] (GPE) cores which assist, and are managed by, the OCC.
 
| [[GPE|General Purpose Engine]] (GPE) cores which assist, and are managed by, the OCC.
 
* The [[SGPE|Stop GPEs]] (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor).
 
* The [[SGPE|Stop GPEs]] (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor).
Line 86: Line 86:
 
|-
 
|-
 
| IOPPE [[HCODE]]
 
| IOPPE [[HCODE]]
−
| [[IOPPE]] cores (on CPU chip)
+
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 +
| [[IOPPE]] cores (on CPU)
 
| [[PNOR|PNOR]] (SPI Flash)
 
| [[PNOR|PNOR]] (SPI Flash)
−
[https://git.raptorcs.com/git/talos-hcode/tree/ Source]
 
 
|
 
|
 
* Involved in CAPI support.
 
* Involved in CAPI support.
 
|- style="background-color:#e0e0e0;"
 
|- style="background-color:#e0e0e0;"
 
| [[OpenBMC]]
 
| [[OpenBMC]]
 +
[https://git.raptorcs.com/git/talos-openbmc/tree/ Source]
 
| BMC chip
 
| BMC chip
 
| BMC SPI Flash
 
| BMC SPI Flash
−
[https://git.raptorcs.com/git/talos-openbmc/tree/ Source]
 
 
|
 
|
 
<small>(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a [[FSP]].)</small>
 
<small>(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a [[FSP]].)</small>

Revision as of 11:12, 30 June 2021

OpenPOWER Firmware is an open-source alternative to OpenFirmware and proprietary IBM firmware used on Power machines.[1] It is a general name for many separate pieces of software used to start recent Power Architecture chips made by IBM.[2]

OpenBMC is a separate project that creates firmware for the Baseboard Management Controller.

Components

Firmware Executed on Loaded from Function
SBE - OTPROM

Source

SBE core (on CPU) OTPROM (on CPU die) The portion of Self-Boot Engine (SBE) firmware permanently written via eFuses into the POWER9 silicon's OTPROM
  • very first instructions executed
  • loads remaining SBE firmware from SEEPROM into SBE core
SBE - SEEPROM

Source

SBE core (on CPU) SBE SEEPROM (on CPU) The portion of Self-Boot Engine (SBE) firmware run from rewritable SEEPROM
  • initialises CPU core
  • loads Hostboot Bootloader
  • backup copy stored on PNOR SPI Flash, used to stage SBE firmware updates
Hostboot Bootloader (HBBL)

Source

CPU core SBE SEEPROM (on CPU)
  • first code which runs on main CPU cores; loads and executes rest of Hostboot
  • responsible for verifying integrity of Hostboot when secure boot is enabled, so this part of Hostboot is stored on the SBE SEEPROM, even though its source code lives inside the Hostboot repository
Hostboot

Source

CPU core PNOR (SPI Flash)
  • initialises DRAM (memory training, zeroing of ECC memory, etc.), processor bus, memory buffers
  • finally, chainloads Skiboot
Skiboot

Source

CPU core PNOR (SPI Flash)
  • initialises PCIe controllers, device trees, real time clock, NVlink, sensors
  • loads OCC firmware and starts OCC running
  • implements OpenPOWER Abstraction Layer (OPAL) for OS runtime services; remains resident in RAM after OS boot
  • finally, chainloads Skiroot
Skiroot/Petitboot

Source

CPU core PNOR (SPI Flash)
  • Skiroot refers to the Linux kernel and initramfs which runs from RAM
  • Contains Petitboot, a userspace application which provides a boot menu
  • Petitboot loads operating system via kexec
OCC firmware

Source

OCC core (on CPU) PNOR (SPI Flash) The On-Chip Controller (OCC) manages:
  • thermal regulation of CPU chip, turbo frequency selection, voltage ID selection, power measurement, etc.
CME HCODE

Source

CME cores (on CPU) PNOR (SPI Flash) The Core Management Engines (CME) are auxillary cores used for power management purposes. They are ultimately responsible to the OCC.
  • There is one CME for every pair of SMT4 cores.
SGPE and PGPE HCODE

Source

SGPE and PGPE cores (on CPU) PNOR (SPI Flash) General Purpose Engine (GPE) cores which assist, and are managed by, the OCC.
  • The Stop GPEs (SGPEs) are part of the mechanism for resuming execution after a STOP instruction is executed (which is a Power ISA instruction which halts the processor).
  • The Pstate GPEs (PGPEs) perform pstate management.
IOPPE HCODE

Source

IOPPE cores (on CPU) PNOR (SPI Flash)
  • Involved in CAPI support.
OpenBMC

Source

BMC chip BMC SPI Flash

(This is not part of OpenPOWER firmware, but is mentioned to give a picture of the division of responsibilities. Not all POWER9 systems use a BMC; IBM systems use a FSP.)

  • Turns system power rails on and off to energise and deenergise CPU modules, RAM, etc.
  • Sends commands to CPU modules over FSI to commence booting.
  • Provides access to PNOR SPI flash containing host firmware via LPC.
  • Receives core temperature information from the OCC; decides and sets fan speeds.
  • Powers off system if OCC indicates catastrophic temperature.
Diagram of main and auxillary cores on POWER9

Process

  1. SBE executes OTPROM, which loads SEEPROM firmware into SBE PIBMEM
  2. SBE executes SEEPROM firmware
  3. OpenBMC uses FSI interface to start SBE
  4. SBE loads Hostboot
  5. Hostboot loads Skiboot
  6. Skiboot loads OCC, Skiroot
  7. Petitboot application within Skiroot loads the operating system
  8. OS talks to firmware through OPAL

References

  1. ↑ Kerr, Jeremy. OpenPOWER: building an open-source software stack from bare metal. LCA 2015 - video on YouTube
  2. ↑ Smith, Stewart. Adventures in OpenPOWER Firmware. LCA 2016 - video on YouTube

See also

External Links

Retrieved from "https://wiki.raptorcs.com/w/index.php?title=OpenPOWER_Firmware&oldid=3506"