Murano

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Revision as of 02:22, 2 February 2018 by Torpcoms (talk | contribs) (add category)
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Package Information
Murano
Processor POWER8
Structure DCM
Maximum base clock -
Maximum turbo clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 3
Maximum PCIe lanes -
Maximum PCIe endpoints -
CAPI interfaces -