Difference between revisions of "Monza"

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(Add navigation to other modules)
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|data14 = 3
 
|data14 = 3
 
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== See Also ==
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* [[Sforza|Sforza]] POWER9 module
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* [[LaGrange|LaGrange]] POWER9 module
  
 
== External Links ==
 
== External Links ==

Revision as of 00:05, 3 May 2020

Package Information
Monza
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 34
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 48
OpenCAPI interfaces 6
NVLink interfaces 3

See Also

External Links