Difference between revisions of "Monza"

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|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces
 
|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces
 
|data11 = -
 
|data11 = -
|label12 = [[OpenCAPI|OpenCAPI]] interfaces
+
|label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes
|data12 = -
+
|data12 = 48
|label13 = [[NVLink|NVLink]] interfaces
+
|label13 = [[OpenCAPI|OpenCAPI]] interfaces
|data13 = -
+
|data13 = 6
 +
|label14 = [[NVLink|NVLink]] interfaces
 +
|data14 = 3
 
}}
 
}}
  
 +
== See Also ==
  
[[Category:Nimbus Modules]]
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* [[Sforza|Sforza]] POWER9 module
 +
* [[LaGrange|LaGrange]] POWER9 module
 +
 
 +
== External Links ==
 +
 
 +
* [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_Monza Monza Module at IBM OpenPOWER portal]
 +
 
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[[Category:Modules]]
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[[Category:POWER9]]

Revision as of 00:05, 3 May 2020

Package Information
Monza
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 34
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 48
OpenCAPI interfaces 6
NVLink interfaces 3

See Also

External Links