Difference between revisions of "Monza"
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|label2 = Processor | |label2 = Processor | ||
|data2 = [[POWER9|POWER9]] | |data2 = [[POWER9|POWER9]] | ||
| − | |label3 = | + | |label3 = Chip |
| − | |data3 = | + | |data3 = Nimbus |
| − | |label4 = Maximum | + | |label4 = Maximum base clock |
|data4 = - | |data4 = - | ||
| − | |label5 = Maximum [[ | + | |label5 = Maximum [[WOF|WOF]] clock |
|data5 = - | |data5 = - | ||
| − | |label6 = | + | |label6 = Maximum [[TDP|TDP]] |
|data6 = - | |data6 = - | ||
| − | |label7 = PCIe | + | |label7 = PCIe controllers ([[PEC|PEC]]) |
| − | |data7 = | + | |data7 = - |
| − | |label8 = | + | |label8 = PCIe generation |
| − | |data8 = | + | |data8 = 4 |
| − | |label9 = Maximum PCIe | + | |label9 = Maximum PCIe lanes |
| − | |data9 = | + | |data9 = 34 |
| − | |label10 = | + | |label10 = Maximum PCIe endpoints |
|data10 = - | |data10 = - | ||
| − | |label11 = [[ | + | |label11 = [[CAPI 2.0|CAPI 2.0]] interfaces |
|data11 = - | |data11 = - | ||
| − | |label12 = [[NVLink|NVLink]] interfaces | + | |label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes |
| − | | | + | |data12 = 48 |
| + | |label13 = [[OpenCAPI|OpenCAPI]] interfaces | ||
| + | |data13 = 6 | ||
| + | |label14 = [[NVLink|NVLink]] interfaces | ||
| + | |data14 = 3 | ||
}} | }} | ||
| + | == See Also == | ||
| − | [[Category: | + | * [[Sforza|Sforza]] POWER9 module |
| + | * [[LaGrange|LaGrange]] POWER9 module | ||
| + | |||
| + | == External Links == | ||
| + | |||
| + | * [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_Monza Monza Module at IBM OpenPOWER portal] | ||
| + | |||
| + | [[Category:Modules]] | ||
| + | [[Category:POWER9]] | ||
