Difference between revisions of "Monza"

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Latest revision as of 07:02, 8 September 2022

Package Information
Monza
Processor POWER9
Chip Nimbus
Maximum base clock -
Maximum WOF clock -
Maximum TDP -
PCIe controllers (PEC) -
PCIe generation 4
Maximum PCIe lanes 34
Maximum PCIe endpoints -
CAPI 2.0 interfaces -
OpenCAPI/NVLink lanes 48
OpenCAPI interfaces 6
NVLink interfaces 3

For more general information about the Nimbus chip this module contains, such as details about particular steppings, please see Nimbus.

Configurations

Known Nimbus-Monza parts
Part Cores Stepping Nest/Boost/Base (GHz) Max
03JM924 24 DD2.3 2.00/3.80/3.150 300 W
02CY598 22 DD2.3 2.00/3.80/3.100 300 W
02CY599 20 DD2.3 2.00/3.80/3.000 250 W
02CY600 18 DD2.3 2.00/3.80/3.450 300 W
02CY601 16 DD2.3 2.00/3.80/3.300 250 W
00NJ261 unknown unknown unknown unknown
00UL016 unknown unknown unknown unknown
00UL017 unknown unknown unknown unknown
00UL018 unknown unknown unknown unknown
00UL020 unknown unknown unknown unknown
00UL021 unknown unknown unknown unknown

Sourced from Monza data sheet v1.5 (see Table 6-10 on page 68) and eBay "power9 monza -lagrange".

See Also

External Links

References