Difference between revisions of "LaGrange"
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|label11 = [[CAPI 2.0|CAPI 2.0]] interfaces | |label11 = [[CAPI 2.0|CAPI 2.0]] interfaces | ||
|data11 = - | |data11 = - | ||
| − | |label12 = [[OpenCAPI|OpenCAPI]] | + | |label12 = [[OpenCAPI|OpenCAPI]]/[[NVLink|NVLink]] lanes |
| − | |data12 = | + | |data12 = 16 |
| − | |label13 = [[NVLink|NVLink]] interfaces | + | |label13 = [[OpenCAPI|OpenCAPI]] interfaces |
| − | | | + | |data13 = 2 |
| + | |label14 = [[NVLink|NVLink]] interfaces | ||
| + | |data14 = 1 | ||
}} | }} | ||
| − | [[Category: | + | '''LaGrange''' is the codename for a POWER9 CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules. |
| + | |||
| + | LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board. | ||
| + | |||
| + | LaGrange will be used for the upcoming RCS [[Condor|Condor]] board, albeit in a single-socket configuration. | ||
| + | |||
| + | {| class="wikitable sortable" | ||
| + | |+ Known Nimbus-LaGrange parts | ||
| + | ! Part | ||
| + | ! Cores | ||
| + | ! Stepping | ||
| + | ! Nest/Boost/Base (GHz) | ||
| + | ! Max | ||
| + | |- | ||
| + | | 02CY069 | ||
| + | | 22 | ||
| + | | | ||
| + | | 2.00/3.80/2.90 | ||
| + | | 225 W | ||
| + | |- | ||
| + | | 02CY254 | ||
| + | | 20 | ||
| + | | | ||
| + | | 2.00/3.80/2.90 | ||
| + | | 225 W | ||
| + | |- | ||
| + | | 02CY249 | ||
| + | | 16 | ||
| + | | | ||
| + | | 2.00/3.80/3.40 | ||
| + | | 225 W | ||
| + | |- | ||
| + | | 02CY057 | ||
| + | | 18 | ||
| + | | | ||
| + | | 2.00/3.80/2.80 | ||
| + | | 190 W | ||
| + | |} | ||
| + | |||
| + | Sourced from [[:File:POWER9 LaGrange ds v17 28MAR2019 pub.pdf|LaGrange data sheet]] (see Table 6-10 on page 66 in version 1.7) | ||
| + | |||
| + | == See Also == | ||
| + | |||
| + | * [[Sforza|Sforza]] POWER9 module | ||
| + | * [[Monza|Monza]] POWER9 module | ||
| + | |||
| + | == External Links == | ||
| + | |||
| + | * [https://www-355.ibm.com/systems/power/openpower/tgcmDocumentRepository.xhtml?aliasId=POWER9_LaGrange LaGrange Module at IBM OpenPOWER portal] | ||
| + | |||
| + | [[Category:Modules]] | ||
| + | [[Category:POWER9]] | ||
Revision as of 12:55, 6 July 2020
| LaGrange | |
|---|---|
| Processor | POWER9 |
| Chip | Nimbus |
| Maximum base clock | - |
| Maximum WOF clock | - |
| Maximum TDP | - |
| PCIe controllers (PEC) | - |
| PCIe generation | 4 |
| Maximum PCIe lanes | 42 |
| Maximum PCIe endpoints | - |
| CAPI 2.0 interfaces | - |
| OpenCAPI/NVLink lanes | 16 |
| OpenCAPI interfaces | 2 |
| NVLink interfaces | 1 |
LaGrange is the codename for a POWER9 CPU module/package; it represents a middle ground between the PCIe-only peripheral connectivity of the the Sforza module, and the maximum OpenCAPI/NVLink connectivity of the Monza module. However, LaGrange also has twice the Xbus (socket-socket) bandwidth of these modules.
LaGrange is used by the Google/Rackspace Zaius/Barreleye G2 board.
LaGrange will be used for the upcoming RCS Condor board, albeit in a single-socket configuration.
| Part | Cores | Stepping | Nest/Boost/Base (GHz) | Max |
|---|---|---|---|---|
| 02CY069 | 22 | 2.00/3.80/2.90 | 225 W | |
| 02CY254 | 20 | 2.00/3.80/2.90 | 225 W | |
| 02CY249 | 16 | 2.00/3.80/3.40 | 225 W | |
| 02CY057 | 18 | 2.00/3.80/2.80 | 190 W |
Sourced from LaGrange data sheet (see Table 6-10 on page 66 in version 1.7)
