Difference between revisions of "POWER8E"
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Without A-bus or SMP over PCIe, the processors in a multisocket configuration instead use X-Bus for SMP. The chip size is 659 mm<sup>2</sup>, rather than 649 mm<sup>2</sup> for POWER8, and only available for the ''S822LC for HPC'', specifically the ''8335-GTB'' model. | Without A-bus or SMP over PCIe, the processors in a multisocket configuration instead use X-Bus for SMP. The chip size is 659 mm<sup>2</sup>, rather than 649 mm<sup>2</sup> for POWER8, and only available for the ''S822LC for HPC'', specifically the ''8335-GTB'' model. | ||
<ref>Caldeira, Alexandre Bicas; Haug, Volker. [https://www.redbooks.ibm.com/redpapers/pdfs/redp5405.pdf IBM Power System S822LC for High Performance Computing Introduction and Technical Overview] (PDF). IBM Redpaper. ISBN 9780738455617.</ref><ref>Gupta, Sumit. [https://www.ibm.com/blogs/systems/ibm-nvidia-present-nvlink-server-youve-waiting/ IBM & NVIDIA present the NVLink server you’ve been waiting for] (HTML). 2016-09-08. IBM IT Infrastructure Blog.</ref> | <ref>Caldeira, Alexandre Bicas; Haug, Volker. [https://www.redbooks.ibm.com/redpapers/pdfs/redp5405.pdf IBM Power System S822LC for High Performance Computing Introduction and Technical Overview] (PDF). IBM Redpaper. ISBN 9780738455617.</ref><ref>Gupta, Sumit. [https://www.ibm.com/blogs/systems/ibm-nvidia-present-nvlink-server-youve-waiting/ IBM & NVIDIA present the NVLink server you’ve been waiting for] (HTML). 2016-09-08. IBM IT Infrastructure Blog.</ref> | ||
| + | |||
| + | == Configurations == | ||
| + | |||
| + | {| class="wikitable sortable" | ||
| + | |+ Known POWER8E parts | ||
| + | ! Part | ||
| + | ! Cores | ||
| + | |- | ||
| + | | 00UL668 | ||
| + | | 10 | ||
| + | |- | ||
| + | | 00UL670 | ||
| + | | 8 | ||
| + | |} | ||
| + | |||
| + | Sourced from [[:File:POWER8 wNVLink DS v1.7 11DEC2017 pub.pdf|POWER8E data sheet v1.7]] (see Table 6-2 on page 65). | ||
== External Links == | == External Links == | ||
Latest revision as of 00:18, 20 September 2022
| POWER8E | |
|---|---|
| Power ISA | 2.07 |
| Process node | 22nm |
| Maximum slices | 12 |
| Maximum cores | 12 SMT8 |
| L2 cache / slice | 512kB |
| L3 cache / slice | 8MB |
| Production availability | 2016 |
| Production stepping(s) | DD2.1 |
| ← POWER8 | POWER9 → |
POWER8E (also known as POWER8 with NVLink, POWER8’ (with a prime symbol), 8335-GTB POWER8, or POWER8+) processors have a different socket than standard POWER8 chips.
Compared to a standard POWER8 Single Chip Module (SCM), the POWER8 with NVLink modifies:
- 2nd CAPP unit added, X2 removed
- x8 PHB
- x8 IOP
- A-bus removed, NVLink added
- NVLink support added in extended ES
- Chip height: 2 C4 rows added
Without A-bus or SMP over PCIe, the processors in a multisocket configuration instead use X-Bus for SMP. The chip size is 659 mm2, rather than 649 mm2 for POWER8, and only available for the S822LC for HPC, specifically the 8335-GTB model. [1][2]
Configurations
| Part | Cores |
|---|---|
| 00UL668 | 10 |
| 00UL670 | 8 |
Sourced from POWER8E data sheet v1.7 (see Table 6-2 on page 65).
External Links
References
- ↑ Caldeira, Alexandre Bicas; Haug, Volker. IBM Power System S822LC for High Performance Computing Introduction and Technical Overview (PDF). IBM Redpaper. ISBN 9780738455617.
- ↑ Gupta, Sumit. IBM & NVIDIA present the NVLink server you’ve been waiting for (HTML). 2016-09-08. IBM IT Infrastructure Blog.
