Difference between revisions of "POWER8"
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Latest revision as of 14:23, 2 March 2019
| POWER8 | |
|---|---|
| Power ISA | 2.07 |
| Process node | 22nm |
| Maximum slices | 12 |
| Maximum cores | 12 SMT8 |
| L2 cache / slice | 512kB |
| L3 cache / slice | 8MB |
| Production availability | November 2015 |
| Production stepping(s) | DD2.0 |
| ← POWER7+ | POWER8E → |
POWER8 is available in Dual Chip Modules (DCM) or Single Chip Modules (SCM); Murano is the DCM and Turismo is the SCM.[1]
POWER8 with NVLink
POWER8 was later altered to support NVLink, this wiki refers to those chips as POWER8E.
External Links
References
- ↑ IIAS - Overview. IBM Knowledge Center. Quote: "The primary compute building block of the Integrated Analytics System is the Power8 S822L Server. This server is based on the Murano DCM chip set. Each processor in the selected configuration provides 12 cores each operating at 3.02 GHz"
